EE WorkbenchPython-native electronics engineering workstation • v2.3.3
Untitled ProjectAnonymous session
Python simulator ready
Start Design Analyze Verify Assist Project
Engineering Overview
Project readiness, workflow, recent results, and recommended next action.
Components
0
Placed schematic devices
Analyses complete
0 / 3
DC • AC • transient
Measurement probes
0
Saved engineering observations
Verification state
Not run
Latest deterministic review

Professional engineering workflow

Follow the evidence chain from design intent to simulation, measured values, verification, and release. You can jump into any step, but later steps are only meaningful when their inputs are complete.
1 · DesignCreate the schematic and define real component/model data.
2 · SimulateEstablish operating point, frequency response, and time-domain behavior.
3 · MeasureTurn waveforms into named engineering quantities and spectral metrics.
4 · VerifyCheck warnings, limits, thermal/noise behavior, PVT and requirements.
5 · Document / ReleaseSave evidence, revision, reports, BOM, models and project package.

What should I do next?

Start or load a circuit
A professional result starts with an explicit circuit and design intent.
Design readiness has not been checked yet.
Readiness looks for duplicate references, missing models, missing ratings, and other sign-off risks.

How to read results

PASS · requirement satisfiedWARNING · review neededFAIL · action requiredNOT VERIFIED · evidence missing

A simulation result is evidence, not automatically a design approval. Use requirements, tolerances, models, operating conditions, SOA/thermal limits and verification history before release.

Conventions: node voltage is referenced to GND unless differential nodes are selected; AC magnitude is small-signal amplitude; phase is degrees; transient time is seconds; power is watts. Engineering prefixes are shown in summaries while raw JSON keeps full numerical precision.

Latest engineering evidence

No analysis or verification evidence yet. Run Simulation to create the first evidence.
Drag symbols • click pin→pin to wire • double-click part to edit • Alt-click pin = probe
Start with a demo on the left or create a blank project.

Selected component

Nothing selected.

Quick add

Current circuit / netlist

Untitled Project
Simulation always runs the project currently open in the schematic. Nothing is simulated unless you start an analysis.

Python-native simulation

Arrow IPC is fast columnar interchange; Parquet uses Zstandard compression for durable evidence.
Anonymous session evidence datasets
Stored server-side per anonymous browser session in Apache Parquet. Metadata is indexed by SQLite WAL. Datasets expire with the anonymous session and are never shared with another browser session.
No stored datasets loaded.
No simulation result yet.
Run DC for bias, AC for frequency response, or transient for waveform behavior.
Raw solver output (full precision)

Waveform / response

Save a plotted trace to compare design revisions or parameter changes.
Interactive cursors ready.
Click the graph to place cursor A/B. The viewer calculates ΔX, ΔY, slope, and 1/Δt for time-domain data.
Run an analysis to display a response.AC uses logarithmic frequency; transient uses linear time. A saved baseline is overlaid for run-to-run comparison.
RF / Signal Integrity / Power Integrity
Analyze imported S-parameters, input match/transmission, Smith-chart position, band-limited TDR, approximate controlled impedance, PDN target impedance, and eye overlays. Every result states where a field solver or protocol-specific sign-off is still required.
Web-native engineering tools

Touchstone · S-parameters

No RF evidence yet.
Import S1P/S2P data or load the demo. The analyzer supports RI, MA and DB Touchstone formats.
Raw RF evidence

Controlled impedance · microstrip

Stackup calculation not run.
This quasi-static calculator is useful for early design. Fabrication sign-off still requires the real stackup and preferably a 2D/3D field solver.
Raw impedance evidence

PDN target-impedance screening

PDN analysis not run.
Target impedance is allowed ripple divided by transient load current.
Raw PDN evidence

Eye diagram from transient simulation

Eye diagram not run.
Uses the cached transient waveform. Protocol masks and receiver models remain external sign-off inputs.
Raw eye evidence
Digital Logic / Timing
Deterministic Boolean/timing screening for browser-based design checks. Use it for combinational truth/timing exploration; HDL event simulation, setup/hold timing and metastability remain outside this lightweight engine.
Deterministic

Logic expression simulator

Logic timing not run.
Supported operators: NOT (~ or not), AND (& or and), OR (| or or), XOR (^).

Timing table / raw evidence

Run the logic simulator to populate the timing table.
Raw digital evidence
AI Engineering Assistant
Your AI key is stored only in the anonymous server session. The AI sees the current project context and can explain, diagnose, suggest measurements, propose optimizations, and generate validation plans. Simulation and verification remain deterministic.
AI not configured

Engineering chat

I can work with the current schematic, simulation results, probes, checks and requirements. Ask me what the circuit does, why a check failed, what to measure, or how to improve a design.
Configure an AI API key in Settings / Integrations to enable natural-language chat.

AI circuit generator

Describe the circuit you want. The AI returns a structured schematic; the Python engine validates connectivity before you can apply it.

No generated circuit yet.

AI optimization

AI proposes candidates; Python evaluates them before you apply anything.
Multi-parameter optimization

AI engineering tools

Let the AI choose a safe deterministic tool, or select one directly. The tool runs on the current project and returns measured results.

No deterministic AI tool run yet.
The assistant may choose or request a tool, but numerical evidence is produced by the deterministic Python engine.
Raw deterministic tool evidence

Current engineering context

No context loaded.

AI working-copy verification

AI suggestions are evaluated on a copy first. Compare the current project against a candidate, then explicitly apply or reject the change.

No candidate comparison run.
The candidate is solved independently and compared with the current design before any change is applied.
Raw candidate-comparison evidence

User measurement probes

Add as many probes as you need. Each probe is saved inside the .eewb project. You can measure differential voltage, component current, power, AC phase/magnitude, or a transient sample. Alt-click a schematic pin to pre-fill a voltage probe.
No probe results yet.
Named probes make numerical evidence repeatable and save it with the project.

FFT / THD

Spectrum not analyzed.
THD compares harmonic energy to the fundamental. Ensure the transient is settled and contains enough coherent cycles for meaningful distortion results.

Measured data import

Import oscilloscope/DMM/data-logger CSV evidence, visualize it, then compare it numerically against a simulation. Imported datasets are saved with the .eewb project.
No measured dataset loaded.
Use CSV with a header row and at least two numeric columns. Non-numeric rows are ignored and reported.
Raw imported-data evidence

Simulation ↔ measurement correlation

Correlation not run.
PASS/FAIL is only assigned when you provide an explicit tolerance. Without one, the comparison remains NOT_VERIFIED evidence.
Correlation numbers

Requirements → evidence

No traceability matrix generated.

Bench instruments · optional SCPI / VISA

When PyVISA and a VISA backend are installed on this PC, EE Workbench can enumerate instruments and issue explicit SCPI queries. On Windows, run install_instruments_windows.bat once for the optional open-source VISA/Python layer; some USB/GPIB instruments still need the vendor VISA driver. Read-only queries are the default; write commands require an explicit allow-write action in the API.
Instrument link not checked.
CSV/lab correlation works without PyVISA. Hardware access depends on the VISA drivers installed on the user's computer.

Professional design review

Enter operating conditions in the units shown. Blank optional fields are treated as not specified; missing evidence is reported rather than assumed to pass.
Design review not run.
A PASS means the implemented checks found no blocking issue; it is not a substitute for missing manufacturer limits or requirements.

Noise analysis

Noise screen not run.
This source-noise estimate is a screening calculation; output-referred sign-off needs transfer functions and validated semiconductor noise data.
Raw noise evidence

Thermal analysis

Thermal screen not run.
Estimated junction temperatures depend on component power and supplied thermal ratings.
Raw thermal evidence

Component library


Live distributor search

Uses your configured provider credentials when available; otherwise the app stays in demo mode. Search is normalized across DigiKey, Mouser and RS.

Custom component editor

Custom components are stored in the .eewb file.

Engineering calculators

Enter SI numbers in the field order shown by the selected formula; results are returned with engineering units.
Choose a formula and enter known values.
The calculator will show the solved quantity first and keep the raw numeric response below for evidence.
Raw calculator result

BOM / lifecycle

Lifecycle risk not analyzed.
Local project metadata can identify missing MPNs, missing datasheets, recorded EOL/NRND status and missing alternates. Live supplier lifecycle/stock still requires supplier data.

Engineering library & verification

Formula calculator

Formula result not calculated.
Results use SI inputs unless a formula states otherwise. Verify that entered values and assumptions match the physical design.
Raw formula result
System self-test not run.
The self-test checks deterministic formulas, simulators and reference cases; it does not replace project-specific verification.
Raw benchmark / self-test evidence

Advanced waveform / analysis tools

No advanced engineering analysis selected.
Run waveform, group-delay, loop-gain, thermal or rating checks to see visual evidence, important metrics and limitations.
Raw advanced engineering evidence

Professional validation matrix

Validation matrix not run.
PVT/model validation results will show their spread, status, and limitations here.
Raw validation data

Python-native SPICE engine

Paste a supported SPICE netlist or generate one from the current schematic. Results are shown as engineering visuals first, with full-precision raw data retained for audit and export.
No SPICE run yet.

The built-in engine supports operating point, AC, transient, DC sweep and a defined SPICE subset. Unsupported constructs are reported explicitly rather than silently ignored.

SPICE result & engineering meaning

No SPICE evidence yet.
Run the netlist to see numerical evidence, visual response, warnings and interpretation.
Operating point uses a node-voltage bar view.
Visual evidence will appear after a successful run.Raw values remain available below.
Raw full-precision solver data
Simulation is engineering evidence, not automatic sign-off. Confirm model provenance, operating conditions, tolerances, safety margins and applicable laboratory/regulatory requirements before release.

Engineering verification suite

Define explicit requirements before release verification. A blank requirement is not tested and must not be interpreted as a pass.

Design requirements

Results

Verification suite not run.
Define requirements above, then run deterministic verification. NOT_VERIFIED means evidence is missing, not that the design passes.
Raw verification / analysis evidence

Complete engineering layer

Deep model, noise, thermal, datasheet and CAD helpers. Advanced analyses use the same visual → meaning → raw evidence pattern as the main simulator.

No advanced analysis selected.
Run noise, FFT, or thermal analysis to see key engineering meaning and a visual result.

Datasheet extraction

Raw advanced-analysis evidence

CAD / PCB helpers

PCB foundation

PCB not initialized.

PCB preview / DRC

PCB evidence not available yet.
Create a board, place/rout objects, then run DRC. A DRC pass checks implemented rules; fabrication sign-off still depends on manufacturer constraints.
Browser 3D view uses board geometry and component courtyard/height metadata; it is a design visualization, not a STEP/MCAD collision solver.

Interactive PCB actions

SPICE model library

Model readiness

Attach verified manufacturer .MODEL/.SUBCKT files to the component or project. The built-in models are generic educational defaults and are not production sign-off models.

Simulation job manager

Long SPICE runs execute as cancellable jobs. Progress is reported by simulation stage. Results stay in this local session until you save the project.

Selected job

Select a job.

Model / library manager

Built-in generic models are available. Vendor libraries are user-supplied.

Model policy

Built-in device models are generic analysis models. Manufacturer libraries can be scanned from a local path or imported into the user's local model store. The software records model names and SHA-256 hashes; it does not copy vendor files into public project bundles unless the user explicitly attaches them.

Encrypted or proprietary model formats are not automatically executed. The native engine accepts supported component parameters and a defined subset of SPICE model syntax for interoperability.

Engineering project

No browser recovery snapshot stored.
Checking anonymous server recovery…
Not saved yet.

Revision / release evidence

No revision baseline captured.
Capture a known state before editing, then compare component, wiring, requirement and PCB changes. Release manifests fingerprint the evidence used for review.
Revision / release raw evidence
Verification history
No verification runs recorded yet.

Attachments / notes / references

Anonymous multi-user web operation
No login is required. Each browser receives an opaque HttpOnly session cookie. SQLite WAL isolates anonymous recovery metadata while large numerical evidence is stored as per-session Apache Parquet. API keys and supplier credentials remain memory-only and are never written to SQLite, Parquet, or .eewb files.
Checking anonymous storage…
The browser session is isolated from other concurrent users.

Supplier API credentials

Credentials entered here are held in memory only by this local Python process. They are not saved into .eewb project files.

DigiKey

Mouser

RS

Status not loaded.

AI assistant

AI credentials are held in memory only and are never written into project files. Local AI servers such as Ollama do not need an API key.

Provider

Choose a cloud provider or a local model server.
Model discovery has not been run.
The AI interprets engineering requests; calculations, simulation, checks and acceptance remain deterministic and are not delegated to the model. Any OpenAI-compatible server can be connected with a custom Base URL.

Environment-variable alternative

EE_AI_PROVIDER=ollama
EE_AI_BASE_URL=http://127.0.0.1:11434
EE_AI_MODEL=your-model
EE_AI_API_KEY=...
OPENAI_API_KEY=...
ANTHROPIC_API_KEY=...
GEMINI_API_KEY=...
DIGIKEY_CLIENT_ID=...
DIGIKEY_CLIENT_SECRET=...
MOUSER_API_KEY=...
RS_API_KEY=...
RS_LOOKUP_URL=...
Environment variables are useful for central deployment. Provider secrets are never exported with a project.